1. Field of the Invention
The present invention relates to a semiconductor memory device and a method thereof, and more particularly, to a ground noise isolation circuit for a semiconductor memory device and a method thereof.
2. Background of the Related Art
FIG. 1 is a circuit diagram of a related art semiconductor memory device which includes a cell array 10, with a plurality of word lines W/L and a plurality of bit lines B/L and /B/L which intersect one another and a plurality of memory cells at the intersections. A word line driver 20 is connected to the word lines W/L for driving a specific word line W/L in accordance with a row address RA, and a bit line sense amplifier 30 amplifies the data outputted from the memory cell to a predetermined level in accordance with the driving of a specific word line. A column switch 40 outputs the data amplified by the bit line sense amplifier 30 to input/output lines I/O and /I/O in accordance with a column selection signal CS of a column decoder (not shown). An I/O amplifier 50 amplifies the data outputted through the column switch 40 and a control block 60 outputs a control signal in accordance with the output of the I/O amplifier 50. A data output unit 70 outputs the output of the control block 60 and the data to an output pad PAD in accordance with a chip enable signal CE.
The word line driver 20 includes a plurality of inverters, each of which includes a PMOS transistor 21 and an NMOS transistor 22. The sources of the NMOS transistors 22 are connected to a word line driver ground line 104 through a resistor R2 and the drains are respectively connected to the word lines W/L1 and W/L2. The bit line sense amplifier 30 is connected to a sense amplifier ground line 103 through a sense amplifier enable driving NMOS transistor 101 and a resistor R1.
The data output unit 70 includes NAND-gates 71 and 72 for NANDing control signals from the control block 60 and a chip enabling signal CE. The inverters 73 and 74 respectively invert the outputs of the NAND-gates 71 and 72, and NMOS transistors 75 and 76 are connected in series between a power supply voltage and an output ground line 102, of which its output terminal is connected to the output pad. In addition, the output ground line 102, the sense amplifier ground line 103, and the word line driver ground line 104 are separated so as to reduce noise which occurs due to ground bouncing, and are connected to a ground combining line 105. The reference characters "a" and "b" denote current flow paths to the surge amplifier and word line ground lines 103 and 104.
The related art semiconductor memory device operates as follows with reference to the word lines W/L1 and W/L2 and bit lines B/Li and /B/Li among the plurality of word lines W/L and the plurality of bit lines B/L and /B/L.
When row address inputs Ra1 and Ra2 are at a low level L and a high level H, respectively, the PMOS transistor 21 and the NMOS transistor 22 of the word line driver 20 are turned on, and the word line W/L1, as shown in FIG. 2A, is selected. The data of the memory cell 11 positioned on the selected word line W/L1 is transferred to the bit line B/Li. A sense amplifier enable signal SAEN becomes active, and the sense amplifier driving transistor 101 is turned on. The bit line sense amplifier 30 amplifies the data carried on the bit line B/Li, as shown in FIG. 2B, and the thusly amplified data is outputted to the input/output lines I/O and /I/O through the column switch 40 in accordance with the activated column selection signal CS.
The data carried on the input/output lines I/O and /I/O is amplified by the I/O amplifier 50 and inputted to the data output unit 70 through the control block 60. The NAND-gates 71 and 72 of the data output unit 70 perform a NAND operation on the chip enable signal CE of a high level and the data outputted from the control block 60 and output the results of the inverters 73 and 74. The inverter 73 outputs a low level signal, and the inverter 74 outputs a high level signal to the NMOS transistors 75 and 76, respectively. Accordingly, the data, as shown in FIG. 2C, is outputted to the output pad through the output terminal of the data output unit 70.
However, since the driving capacity of the data output unit 70 is very high, and when the NMOS transistor 76 of which its source is connected to the output ground line 102 is turned on, the output is instantly bounced, as shown in FIG. 2C, in accordance with the virtual inductance of the lead frame. The ground bouncing induces another ground bouncing of the ground combining line 105 through the output ground terminal 102, as shown in FIG. 2D, and the ground bouncing of the ground combining line 105 causes a ground bouncing noise in the sense amplifier ground line 103, and the word line driver ground line 104. Further, in addition, the ground bouncing noise, which occurs in the sense amplifier ground line 103 and the word line driver ground line 104, is inputted to the bit line sense amplifier 30 and the word line driver 20 at a time difference in accordance with the difference between the resistors R1 and R2. The bit line /B/Li at the time t1 is shown in FIG. 2B, and the non-selected word line W/L2 at the time t2 is shown in FIG. 2A.
Therefore, the wave forms at the node "A" of the non-selected word line W/L2 and the node point "B" of the bit line /B/Li are shown in FIGS. 2E and 2F, respectively. The electrical potential difference Vgs at the nodes "A" and "B" at the time t1, i.e., the voltage difference between the gate and source of a transmission transistor of the memory cell 12 is .DELTA.V, as shown in FIG. 2F.
If the electrical potential difference (Vgs=.DELTA.V) between the gate and source of the transmission transistor of the non-selected memory cell 12 is greater than the threshold voltage Vth of the transmission transistor, the non-selected memory cell 12 is turned on parasitically, which cause an erroneous reading or writing of the data of the selected memory cell.
In the related semiconductor memory device, when the data is changed from a high level to a low level by the data output unit due to the noise which occurs by the ground bouncing to affect the bit line through the sense amplifier ground line and sense amplifier, the transmission transistor of the non-selected memory cell may be turned on, thus resulting in erroneous data reading or writing of the memory cell.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.